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AR# 31190

10.1 EDK SP2, xps_ll_temac_v1_01_a - With SGMII, when using the 125 MHz ref clock for the MGT in Virtex 4, the MGT PLL doesn't lock

Description

For SGMII interface, when using the 125 MHz ref clock for the MGT as noted in the LL temac data sheet, the MGT PLL doesn't lock. But according to the Virtex-4 temac user guide (UG074), a 250 MHz clock should be used instead.

Solution

The latest xps_ll_temac_v1_01_b data sheet has been updated and published in EDK 10.1 SP2 release to indicate that the clock should be 250 MHz for Virtex 4. It also provides an example set of constraints for the system.ucf file to allow use of a 125 MHz clock which was tested on an ML405 system.  

 

These issues have been fixed in the latest release in EDK 10.1 Service Pack 2 available at: 

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

AR# 31190
Date Created 06/17/2008
Last Updated 05/22/2014
Status Archive
Type General Article