Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Interrupt Status bit not set when generating Legacy Interrupt
Description
Known Issue: v1.10, v1.9, v1.8, v1.7.1, v1.6.1, v1.5.2, v1.5.1, v1.5, v1.4, v1.3, v1.2, v1.1
When generating a Legacy Interrupt, the Endpoint Block Plus Wrapper does not set the Interrupt Status bit within the Device Status register. Why?
Solution
The interrupt status bit is bit 3 of the Device Status Register, located at Offset 06H in the Endpoints Type0 configuration space. This bit should be set when a legacy interrupt is generated to indicate that an interrupt is pending internally in the device. The Endpoint Block Plus solution does not set this bit correctly when the application generates a legacy interrupt on the CFG interface.
The system software uses this bit to identify the interrupting device in a scenario where multiple interrupt vectors are collapsed upstream.
There is no work-around at this time. However, this issue has not been known to cause any system problems by customers.
The v1.11 release User Guide now includes a note on this issue in the Interrupt Generation section.
Revision History
06/24/2009 - Update that v1.11 UG includes information
04/13/2009 - Update for ISE 11.1 release
09/10/2008 - Updated to reflect v1.9.
07/14/2008 - Changed title.
06/18/2008 - Initial Release of AR.
Applies To
IP
- Endpoint Block Plus Wrapper for PCI Express