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AR# 3122

CPLD XC9500/XL/XV, CoolRunner-II/XPLA3 - How do the GSR, BUFG, and OE buffers work?


Keywords: BUFGSR, global, dedicated, routing

Urgency: Standard

General Description:
How do the Global Set/Reset (GSR), Global Clock (GCK), and Global Tri-state (GTS) operate? Do they use dedicated routing? Do they globally connect to all flip-flops in a design (as occurs in FPGAs)? How do I connect them? Is there a way to force the utilization of global routing?


The GSR must be connected to all of the registers that you want the signal to go to in your design. This is different from FPGAs in which using the STARTUP block and connecting to the signal GSR globally sets/resets all flip-flops on the device.

The GSR can be added to the device by either direct instantiation of the component (BUFGSR for global set/reset, BUFG for global clock, and BUFGTS for global tri-state) or by using a UCF constraint. For more information, see (Xilinx Answer 10453).

The GSR uses dedicated routing if there is no logic (other than an inverter) between the GSR pin and the register. This allows the ISE tools to use the dedicated routing on the device. The GSR can be connected to either the Set or the Reset port of any registers in the device.

You can confirm global routing usage by reading the CPLD fitter report, as shown in the following section from a CPLD fitter report:

"Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused."

The global clock and tri-state buffers operate in the same manner.

For other common CPLD questions, see the Tech Tips FAQ for Xilinx CPLDs at:
AR# 3122
Date Created 11/25/1997
Last Updated 11/29/2005
Status Active
Type General Article