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AR# 31251

Virtex-5 GTP RocketIO - Pipelining CHBONDI/O to work around timing failures


In some channel-bonded applications, it may be necessary to pipeline the CHBONDO/I signals between GTP/X tiles in order to meet timing. The most common case where this would be necessary is if there is a number of GTP/X tiles separating those being channel bonded. We do recommend that channel-bonded lanes occupy consecutively located GTP tiles. You should be aware that this solution has not been fully tested, though it has been seen to operate in both Aurora v2.9 and XAUI 7.3.


If timing is not being met on the CHBONDO to CHBONDI path between sequential channel bonding levels, it is possible to pipeline this path. The following steps must be followed to ensure correct operation in both simulation and hardware.

1. Add registers into the CHBONDO-CHBONDI path, making sure that they are clocked by RXUSRCLK. This is similar to any other pipelining application.

2. Add 1 to the CHAN_BOND_LEVEL attribute for all of the higher leveled GTP/Xs on the CHBONDO side of the registers. For example, in a 4 lane application if pipelining was required between the transceiver with CHAN_BOND_LEVEL = 2 and the transceiver with CHAN_BOND_LEVEL = 1, the higher leveled transceivers with CHAN_BOND_LEVEL = 2 and 3 will need to be modified to 3 and 4 respectively.

3. For simulation to run correctly, a delay of 100 ps will need to be added between to the output data from the pipeline registers. This is necessary to compensate for delays internal to the GTP/X models and will not be synthesized.

4. GTX Only: Add 1 to both the CLK_COR_MIN_LAT_0/1 and CLK_COR_MAX_LAT_0/1 attributes for each transceiver which required an increased CHAN_BOND_LEVEL.

Here is a visualization of the changes necessary:

Pipeline Structure
Pipeline Structure

AR# 31251
Date Created 07/11/2008
Last Updated 12/15/2012
Status Active
Type General Article