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AR# 31263: LogiCORE Viterbi Decoder v6.2 - Why does the latency in simulation not match up with the latency equations in the data sheet?
LogiCORE Viterbi Decoder v6.2 - Why does the latency in simulation not match up with the latency equations in the data sheet?
When performing a simulation, the latency does not equal the latency equation in the data sheet.
The latency of the Viterbi Decoder depends on the parameters associated with the core (e.g., traceback length, constraint length, and best state). The latencies provided in the data sheet are a count of the number of symbol inputs between DATA_IN with associated CE, and the decoded data result output on DATA_OUT validated by the RDY signal.
At present, the equations in the data sheet do not match up with the latencies found during simulation. The total latency figure is dependent on other factors (such as Best State, Speed Optimization, etc.); therefore, to obtain the total latency, the decoder should be simulated.
The above information will be included in a future release of the data sheet.
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