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AR# 31268

10.1 EDK, MPMC v4.01.a - MPMC hangs when read or write data path FIFOs disabled


When disabling the MPMC read or write data FIFOs, using C_PI<Port_Num>_RD_FIFO_TYPE or C_PI<Port_Num>_WR_FIFO_TYPE set to 'DISABLED', the MPMC hangs. How do I resolve this issue?


Re-enabling the read and write FIFOs will work around this issue. 


Alternatively, the source can be modified to fix this issue. Start by copying the entire MPMC pcore to the project directory and modifying the "hdl/verilog/mpmc_data_path.v" as follows: 


Read FIFO disabled 

From (line 491 in MPMC v4.02.a): 

assign DP_Ctrl_RdFIFO_AlmostFull[i] = 1'b1; 

assign PI_RdFIFO_RdWdAddr_FIFOFull[i] = 1'b1; 


assign DP_Ctrl_RdFIFO_AlmostFull[i] = 1'b0; 

assign PI_RdFIFO_RdWdAddr_FIFOFull[i] = 1'b0; 


This read FIFO issue is fixed starting in MPMCv4.03.a, released in EDK 10.1 Service Pack 3. 


Write FIFO disabled 

From (line 165 in MPMC v4.03.a): 

assign DP_Ctrl_WrFIFO_Empty[i] = 1'b1; 

assign PI_WrFIFO_AlmostFull[i] = 1'b1; 


assign DP_Ctrl_WrFIFO_Empty[i] = 1'b0; 

assign PI_WrFIFO_AlmostFull[i] = 1'b0; 


Xilinx plans to fix the write FIFO issue in the latest version of MPMC released in EDK 11.1.

AR# 31268
Date 05/22/2014
Status Archive
Type General Article
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