When simulating a Virtex-5 FPGA System Monitor, the outputs of simulation (alarms, as well as the measurement results in the status registers) are not changing to reflect the value in the Analog Stimulus file.
This issue occurs when there is a space before the carriage return of the Analog Stimulus file. If there is a space, the subsequent values are not passed to the simulator, so the outputs of the simulation never change.
To work around the issue, delete the space and ensure that there is a carriage return directly after the last item on the first line (excluding any comment lines).
This issue only occurs in a VHDL simulation.