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AR# 31282

10.1 EDK SP3, xps_ll_temac v1.01.b - Soft TEMAC based design timing considerations for 1000 Mb/s mode in Spartan-3 devices


Special clocking requirements must be considered for using the XPS LL TEMAC in the "soft" mode when running at the 1000 Mb/s mode.

This Answer Record is primarily intended to supplement the information found in the "Soft TEMAC GMII Constraints for Spartan-3A FPGA devices" when using the xps_ll_temac in Spartan-3 devices. For Virtex-5 and Virtex-4 designs that use the soft mode, refer to the sections of xps_ll_temac data sheet.


As the xps_ll_temac utilizes the soft Tri-Mode Ethernet LogiCORE when used in the "soft" mode, please refer to the LogicCORE Tri-Mode Ethernet MAC User Guide, UG138. Appendix D of this user guide contains a section called "DCM Phase Shifting Requirements". This section contains details on meeting the setup and hold time requirements for the RX_CLK and RX_DATA. Following is this section from the user guide:

Appendix D: Calculating the DCM Phase Shift

DCM Phase Shifting Requirements

A DCM is used in the receiver clock path to meet the input setup and

hold requirements when implementing GMII/MII using the core in

Spartan-3, Spartan-3E, and Spartan-3A devices (see "Implementing

External GMII" on page 63). In RGMII, a DCM is used to maintain the

setup and hold times in all devices, except Virtex-5 and Virtex-4

(see "RGMII Receive Clock Generation" on page 122). In these cases,

a fixed-phase shift offset is applied to the receiver clock DCM to

skew the clock; this performs static alignment by using the receiver

clock DCM to shift the internal version of the receiver clock such

that the data is sampled at the optimum time. The ability to shift

the internal clock in small increments is critical for sampling

high-speed source synchronous signals. For statically aligned

systems, the DCM output clock phase offset (as set by the phase shift

value) is a critical part of the system, as is the requirement that

the PCB is designed with precise delay and impedance-matching for all

the GMII receiver data bus and control signals. You must determine

the best DCM setting (phase shift) to ensure that the target system

has the maximum system margin to perform across voltage, temperature,

and process (multiple chips) variations. Testing the system to

determine the best DCM phase shift setting has the added advantage of

providing a benchmark of the system margin based on the UI (unit

interval or bit time). System margin is defined as the following:

System Margin (ps) = UI(ps) * (working phase shift range/128)

Finding the Ideal Phase Shift Value

Xilinx cannot recommend a singular phase shift value that is

effective across all hardware platforms. Xilinx does not recommend

attempting to determine the phase shift setting empirically. In

addition to the clock-to-data phase relationship, other factors such

as package flight time (package skew) and clock routing delays

(internal to the device) affect the clock to data relationship at the

sample point (in the IOB) and are difficult to characterize. Xilinx

recommends extensive investigation of the phase shift setting during

hardware integration and debugging. The phase shift settings provided

in the example design constraint file are placeholders, and work

successfully in back-annotated simulation of the example design.

Perform a complete sweep of phase shift settings during your initial

system test. Use only positive (0 to 255) phase shift settings, and

use a test range that covers a range of no less than 128,

corresponding to a total 180 degrees of clock offset. This does not

imply that 128 phase shift values must be tested; increments of 4

(52, 56, 60, and so forth) correspond to roughly one DCM tap, and

consequently provide an appropriate step size. Additionally, it is

not necessary to characterize areas outside the working phase shift

range. At the edge of the operating phase shift range, system

behavior changes dramatically. In eight phase shift settings or less,

the system can transition from no errors to exhibiting errors.

Checking the operational edge at a step size of two (on more than one

board) refines the typical operational phase shift range. Once the

range is determined, choose the average of the high and low working

phase shift values as the default. During the production test, Xilinx

recommends that you re-examine the working range at corner case

operating conditions to determine whether any final adjustments to

the final phase shift setting are needed. You can use the FPGA Editor

to generate the required test file set instead of resorting to

multiple PAR runs. Performing the test on design files that differ

only in phase shift setting prevents other variables from affecting

the test results. FPGA Editor operations can even be scripted

further, reducing the effort needed to perform this characterization.

(Tri-Mode Ethernet MAC v3.5 User Guide, UG138 March 24, 2008)

For further details regarding clocking for the LogiCORE Tri-Mode Ethernet MAC soft IP, see the LogicCORE Tri-Mode Ethernet MAC User Guide (UG138), which is installed with ISE and CORE Generator, and is placed in the "doc" folder when you generate this core with CORE Generator.

Alternatively, you can download the user guide from the lounge. The lounge entrance is located at:


AR# 31282
Date Created 09/26/2008
Last Updated 12/15/2012
Status Active
Type General Article