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AR# 31284

Endpoint Block Plus Wrapper v1.9 for PCI Express - Per Vector Masking Bit incorrectly set inside MSI Control Register


Known Issue: v1.9, v1.8, v1.7, v1.6, v1.5, v1.4, v1.3, v1.2, v1.1  
Why is the Per Vector Masking Bit incorrectly set to 1'b1 inside the MSI Control register?


The MSI Control register is located within the MSI Capability structure at 048H inside the Endpoint's configuration space. Bit 8 within the MSI Control register is the Per Vector Masking bit, and it is always set to 1'b1. Per Vector Masking is an optional supported feature of MSI as defined in section of the PCI v3.0 specification. As a result, the Block Plus Core does not support Per Vector Masking.

Fabric does not have access to this bit; therefore, no fix is planned.

Currently, no system interoperability issues have been encountered due to this bit being set.

Revision History 
03/05/2009 - Updated that this is an optional feature in MSI rather than not supported as was originally stated 
07/09/2008 - Initial release

AR# 31284
Date Created 09/09/2008
Last Updated 08/26/2013
Status Active
Type General Article
  • Virtex-5 Integrated Endpoint Block