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AR# 31287

XAPP1122 - Parameterizable 8b/10b Encoder v1.1 Release Notes and Known Issues


This Release Notes and Known Issues Answer Record is for XAPP1122 - Parameterizable 8b/10b Encoder v1.1 released on November 10, 2008, and contains the following information:
  • General Information
  • New Features
  • Bug Fixes
  • Known Issues

XAPP1122 is a source code replacement for the "LogiCORE 8b/10b Encoder v5.0" from the CORE Generator software.


General Information
This Answer Record describes the 8b/10b Encoder Reference Design v1.1 source code. The application note that accompanies this design is (Xilinx XAPP1122). This application note describes the implementation of an 8b/10b encoder, which encodes 8-bit words into 10-bit DC-balanced symbols. The reference design is based on the ISE CORE Generator 8b/10b Encoder v5.0 LogiCORE IP netlist core. Supported device families for this reference design are: Virtex-II, Virtex-II Pro, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP, Virtex-4, Virtex-5 and newer architectures.
New Features
  • Virtex-5 device support
  • Spartan-3E device support
  • Spartan-3A device support
  • Default initialization values have been assigned to the Encoder ports and signals. These values dictate the initial state of the design on power-up. The initial values for DOUT, DOUT_B, DISP_OUT, and DISP_OUT_B are assigned by the generics C_FORCE_CODE_VAL, C_FORCE_CODE_VAL_B, C_FORCE_CODE_DISP, and C_FORCE_CODE_DISP_B, respectively. The default for all other ports and signals is 0.

Resolved Issues
These issues were originally Known Issues from the LogiCORE 8b/10b Encoder v5.0:
  • Core contains incompletely specified RLOCs
  • Version found: v4.0 (LogiCORE IP core)
  • Version fixed: v1.1
  • CR 325690: RLOCs were removed to improve portability between architectures
  • Priority of CE signal over FORCE_CODE when initializing registers is inconsistent.
  • Version found: v5.0 (LogiCORE IP core)
  • Version fixed: v1.1
  • CR 476991

Known Issues
  • None

General Recommendations
  • The encoder inputs DIN, KIN, FORCE_CODE, and FORCE_DISP should be kept in alignment with each other by clocking the signals on the same clock edge.

Doubling the 8b/10b datapath width to 16b/20b with the two-encoder configuration
  • The two-encoder configuration in Figure 4 illustrates one method of doubling the 8b/10b datapath width to 16b/20b. In this diagram (and in the preceding verbiage), it advises the user to make sure the data (DIN) changes right before the active (rising) edge of the LSB encoder clock.
  • The application note recommends a register clocked on the falling edge to accomplish this. In the diagram, this suggested register is drawn for DIN only. However, since the other inputs are related to the data, they must be kept in alignment with DIN.
  • If DIN is registered on the falling edge as shown in Figure 4 of(Xilinx XAPP1122), it is recommended that KIN and FORCE_CODE also be registered on the falling edge before encoding as well.

Revision History
10/31/2008 - Initial Release
AR# 31287
Date 12/15/2012
Status Active
Type General Article
  • 8b/10b Decoder
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