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AR# 31288

XAPP1112 - Parameterizable 8b/10b Decoder v1.1, Release Notes and Known Issues


This Release Notes and Known Issues Answer Record is for XAPP1112 - Parameterizable 8b/10b Decoder v1.1 released on October 31, 2008, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

XAPP1112 is a source code replacement for the "LogiCORE 8b/10b Decoder v7.1" from CORE Generator.


General Information

This Answer Record describes the 8b/10b Decoder Reference Design v1.1 source code. The application note that accompanies this design is (Xilinx XAPP1112). This application note describes the implementation of an 8b/10b Decoder, which decodes DC-balanced symbols that have been encoded by an 8b/10b encoder. The Reference Design is based on the ISE CORE Generator 8b/10b Decoder v7.1 LogiCORE IP netlist core. Supported device families for this reference design are: Virtex-II, Virtex-II Pro, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP, Virtex-4, Virtex-5, and newer architectures.

New Features

- Virtex-5 support

- Spartan-3E support

- Spartan-3A support

- Default initialization values have been assigned to the Decoder ports and signals. These values dictate the initial state of the design on power-up. The initial values for DOUT, DOUT_B, KOUT, KOUT_B, RUN_DISP, RUN_DISP_B, SYM_DISP, and SYM_DISP_B are assigned by generics. The default for all other ports and signals is 0.

Resolved Issues

These issues were originally Known Issues from the LogiCORE 8b/10b Decoder v7.1:

- DISP_ERROR of the LUT-based Decoder still transitions when CE = 0.

- Version found: v7.1 (LogiCORE IP core)

- Version fixed: v1.1

- CR 325672, 442826

- Priority of CE signal over SINIT when initializing registers is inconsistent.

- Version found: v7.1 (LogiCORE IP core)

- Version fixed: v1.1

- CR 476990

Known Issues

- None

Revision History

10/31/2008 - Initial Release

AR# 31288
Date Created 11/05/2008
Last Updated 02/21/2013
Status Active
Type General Article