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AR# 31290

LogiCORE Endpoint PIPE v1.7 for PCI Express - Example Design returns "ERROR:Place:1018 " during MAP phase in ISE 10.1 SP2/SP3

Description

When running the provided "implement.bat" script to implement the PIPE core's Example Design, the following error occurs during MAP:

ERROR:Place:1018 - A clock IOB / clock component pair have been found that are

not placed at an optimal clock IOB / clock site pair. The clock component

<endpoint_pipe_v1_7/BU2/U0/pci_exp_1_lane_epipe_ep0/plm/kh2_mgt/special_bufg>

is placed at site <BUFGMUX_X2Y11>. The IO component <rxclk> is placed at site

<B11>. This will not allow the use of the fast path between the IO and the

Clock buffer. If this sub optimal condition is acceptable for this design,

you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote

this message to a WARNING and allow your design to continue. However, the use

of this override is highly discouraged as it may lead to very poor timing

results. It is recommended that this error condition be corrected in the

design. A list of all the COMP.PINs used in this clock placement rule is

listed below. These examples can be used directly in the .ucf file to

override this clock rule.

< NET "rxclk" CLOCK_DEDICATED_ROUTE = FALSE; >

Solution

In previous versions of ISE (before 10.1.02), this ERROR was a WARNING, so the implementation phase was not halted. Due to changes in the ISE 10.1.02 design tools, this is now an Error. This Error could occur in any PIPE core design, not just the Example Design.

For the Endpoint PIPE v1.7 Core, it is acceptable to use the UCF constraint suggested in the Error message to demote this to a Warning:

NET "rxclk" CLOCK_DEDICATED_ROUTE = FALSE;

Revision History

09/19/2008 - Initial Release

AR# 31290
Date Created 09/09/2008
Last Updated 12/15/2012
Status Active
Type General Article