11.1 System Generator for DSP - Why is the reset signal on my FIFO not behaving the same in hardware as in software?

问答编号#	31294	搜索另一个问答
专题	SW-SysGen
最后更新	2009/04/15
记录状态	Active

疑问描述

Keywords: FIFO Generator, level, edge, sensitive

In System Generator simulation, the reset behaves as a level-sensitive signal. However, in HDL simulation (and in hardware), it is edge-sensitive.

解决方案

This is due to a change of behavior in the FIFO Generator IP Core which is used for the FIFO Block in System Generator for DSP. The new behavior is that the reset signal is edge-sensitive, which has not been reflected in System Generator.

This will be addressed in a future release of System Generator.