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AR# 31298

LogiCORE PCI v3.165 - "ERROR:PhysDesignRules:1719 - Incomplete connectivity..."


The following type of error occurs in XDL when I run the command line script to implement a 66 MHz Xilinx PCI Core targeting a Spartan device:

"ERROR:PhysDesignRules:1719 - Incomplete connectivity. The pin <Y> of comp block <TIME_OUT> is used and partially connected to network <PCI_CORE/PCI_LC/MASTER/LAT_TIMR/TC>. All networks must have complete connectivity through out the comp hierarchy and the connectivity for this pin must be removed or completed."

The instance path in the error might vary.


Xilinx Spartan 66 MHz PCI solutions require the use of a Perl script to re-route timing critical paths within the design. XILPERL is called automatically in "run_xilinx.sh," and the error message defined above will be outputted when building in certain environments.

This error should arise only when implementing a 66 MHz PCI v3.165 solution targeting a Spartan-3/3E/3A Device. This error is also seen only when running implementation using the 64-bit ISE tools. Running the run_xilinx.bat (Windows) or run_xilinx.sh(Linux) using the 32-bit ISE tools will successfully complete.

To work around this issue, use the 32-bit ISE tools to build the design.

Revision History

07/14/2008 - Initial Release

AR# 31298
Date Created 09/09/2008
Last Updated 12/15/2012
Status Active
Type General Article