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AR# 31302

LogiCORE 3GPP LTE Turbo Decoder v1.0 - Why doesn't the VHDL/Verilog Structural simulation work?


When using a Verilog structural model with a VHDL, or Verilog, top level, I find that there is no output on the LTE Decoder.


The behavior of the UniSim library during GSR is different for VHDL and Verilog.

In Verilog, FD components are held at their INIT state during GSR regardless of the user clock. In VHDL the INIT value is applied at the start of the GSR, but the next user clock immediately changes the Q output to that on the D input even if the GSR signal is still High.

Similarly, but reversed, VHDL SRLs ignore the user clock during GSR, while Verilog starts clocking as soon as the user clock starts.

The combination of the two effects leaves a SRL16 prescaler undefined, causing the scheduler to become inactive.

The easy work-around is to hold the user clock inactive for the first 200 ns of simulation waiting for GSR to release. Example code is below:


--Generate clock




wait for 200 ns;


wait for clk_period/2;

clk <= not clk;

end loop;

end process;

AR# 31302
Date 02/19/2013
Status Active
Type General Article
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