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AR# 31317

9.2i EDK, MPMC2 v1.7 - Data is corrupted on a double word write access across NPI interface

Description

Keyword: invalid, error

I have been simulating a new MPMC2 design which uses double word accesses to/from memory on an NPI port. Data is corrupted on the write access.

How do I resolve this issue?

Solution

The problem is the timing of the 'dbl_word_transaction' signal on the BRAM which incorrectly causes 'push_toggle' (in write_fifo_bram.v) to toggle for double word transactions. To work around this issue, please modify the mpmc2_write_fifo.v file as shown below:

// make the BRAM FIFOs

else

begin : use_BRAMs

write_fifo_bram

#(

.C_FAMILY (C_FAMILY),

.C_NUM_BRAM (C_WRITE_FIFO_NUM_BRAM),

.C_WRITE_FIFO_MEMORY_WIDTH (C_WRITE_FIFO_MEMORY_WIDTH),

.C_WRITE_FIFO_PORT_WIDTH (C_WRITE_FIFO_PORT_WIDTH),

.C_WRITE_FIFO_APP_PIPELINE (C_WRITE_FIFO_APP_PIPELINE),

.C_WRITE_FIFO_MEM_PIPELINE (C_WRITE_FIFO_MEM_PIPELINE)

)

wrfifo_bram

(

.CLK_bram_mem_side (CLK_mem_side),

.CLK_bram_app_side (CLK_app_side),

.CLK2X_bram_mem_side (CLK2X_mem_side),

.CLK2X_bram_app_side (CLK2X_app_side),

.reset (Rst || reset_fifo),

.push (push),

.pop (pop),

.app_data_in (app_data_to_fifo),

.app_be_in (app_be_to_fifo),

.mem_data_out (fifo_data_to_tml),

.mem_be_out (fifo_be_to_tml),

.dbl_word_transaction (dbl_word_transaction_i), // IB Changed 17/06/08 - 'dbl_word_transaction_i_d1' is one cycle to late for a double word access!

// .dbl_word_transaction (dbl_word_transaction_i_d1),

.which_dbl_word (which_dbl_word)

);

This issue does not affect MPMC v3 and later.

AR# 31317
Date Created 09/23/2008
Last Updated 12/15/2012
Status Active
Type General Article