We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31379

LogiCORE FIFO Generator v4.3 - Cannot change read/write clock frequencies with Built-in FIFO when importing an XCO file


Keywords: LogiCORE, CORE Generator, IP, update, 10.1, FIFO, FIFOGen, Independent Clocks, Built-in FIFO, Read Clock Frequency, Write Clock Frequency

Importing a FIFO Generator v4.3 XCO file into a Virtex-4 CORE Generator project can cause unexpected behavior in the GUI. Specifically, on page 1 of the customization wizard, if you change the FIFO type to "Independent Clocks (RD_CLK, WR_CLK) Built-in FIFO," page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency as user options.

This happens when the imported XCO file has an incorrect range in the Write Width for the Built-in FIFO.


After importing the XCO file, perform the following:

1. Go directly to page 2 of the FIFO Generator wizard (do not change anything on page 1).
2. Change the "Write Width" to a value in the range of 4, 9, 18, or 36.
3. Go back to page 1 and select the Built-in FIFO with Independent Clocks.

You should now be able to edit the Read and Write clock frequencies in the Built-in FIFO Options on page 2.

Revision History
08/26/2008 - Initial Release
AR# 31379
Date Created 07/21/2008
Last Updated 08/25/2008
Status Active
Type General Article