Description
Keywords: DCM, Unisim, Simprim, Spartan, DCM_SP
The clock output from DCM is irregular when the input clock to the DCM simulation model has jitter. Why?
Solution
This is a limitation with the simulation model only. Even though the input clock jitter is within the specification, DCM simulation model will not be able to handle the input clock jitter stimulus when "clkout_phase_shift " is set to Variable.