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AR# 31413

9.1 Virtex-4 MAP - Timing constraints may be dropped from paths transformed by Physical Synthesis MAP options


A problem has been identified where timing constraints are lost when the Physical Synthesis options "-global_opt on" and "-retiming on" are used together. Specifically, the problem occurs when FFs are transformed to a Shift Register (SRL) and as a result the path to the SRL is unconstrained. SRL transformation constraints can occur with global_opt alone, but are more likely to occur if retiming is also used.


This problem is scheduled to be fixed in ISE version 11.1. Meanwhile, if Physical Synthesis options are used, it is advised that the resulting implementation be analyzed for unconstrained paths. 


The design exhibiting this issue in ISE version 9.1i did not exhibit the issue in ISE 10.1, and it was also noted that no SRL transformations took place. ISE 10.1 is less likely to perform SRL transformations than 9.1i because of a change that eliminated some suboptimal transformations from occurring. For that reason, timing paths are less likely to be affected in 10.1 than in 9.1i.

AR# 31413
Date Created 07/31/2008
Last Updated 05/21/2014
Status Archive
Type General Article
  • ISE - 9.1i
  • ISE - 10.1