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AR# 31419

LogiCORE Endpoint Block Plus for PCI Express - ML555 not recognized by system. What is the pinout for the ML555 board?

Description

The Endpoint Block Plus Core downloaded to the ML555 board is not recognized by the system.

Solution


The default UCF file generated for v1.8 and later cores changed. The new locations are:

NET "sys_clk_p" LOC = "P4" ;
NET "sys_clk_n" LOC = "P3" ;

ML555 needs following clock location:

NET "sys_clk_p" LOC = "Y4" ;
NET "sys_clk_n" LOC = "Y3" ;


The complete ML555 pinout for the Endpoint Block Plus Core is below. Replace the appropriate lines in the generated UCF file.

NET "sys_reset_n" LOC = "AE14" | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;

NET "sys_clk_p" LOC = "Y4" ;
NET "sys_clk_n" LOC = "Y3" ;
INST "refclk_ibuf" DIFF_TERM = "TRUE" ;

# PCIe Lanes 0, 1
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y2;
# PCIe Lanes 2, 3
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTP_DUAL_X0Y1;
# PCIe Lanes 4, 5
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" LOC = GTP_DUAL_X0Y3;
# PCIe Lanes 6, 7
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" LOC = GTP_DUAL_X0Y0;

Revision History
09/09/2008 - Initial Release
AR# 31419
Date Created 09/09/2008
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Virtex-5 Integrated Endpoint Block