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AR# 3142

TAENGINE M1.3 - ERROR:hi402 there is no original clock signal to clock pin *.CLKF


Keywords: taengine, cpld, 9500, m1.3, hi402, error

Urgency: standard

General Description:

Customer has a cpld design that they want to produce timing sim data for. In m1.3 the design will translate and fit with no problems. But then the taengine is executed and right away the flow engine stops and the design manager will report that the deign was timed with errors. If you open the timing report it is blank. The last line of the fe.log is :

taengine -f design -l design.tim


This error has been found in the M1.3 release with all the latest patches,
however the problem has been fixed in the M1.4 release.
AR# 3142
Date Created 12/01/1997
Last Updated 03/29/2000
Status Archive
Type General Article