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AR# 31431

10.1EDK SP3, plbv46_pcie_v3_00_a - Un-encrypt (VHDL/Verilog) source code for plbv46 PCIe bridge


Due to the migration of the core from the original (now discontinued) Block wrapper to the v1.8 Block Plus wrapper, we were forced to encrypt the full core. The bridge files that we do not need to encrypt are included in the zip file attached to this Answer Record.

In EDK 11.1 The Block Plus wrapper files are split from the main bridge core and only the Block Plus wrapper portion of the design will be encrypted.


You can download the un-encrypted files from:


Please create a local pcore named "plbv46_pcie_v3_00_a" and unzip the VHDL/Verilog in this attachment into the appropriate directories. Close and Re-Open the EDK project.

These files will be include in the plbv46_pci_v1_03_a version in the next EDK11.1 release, available at:


AR# 31431
Date Created 09/12/2008
Last Updated 12/15/2012
Status Active
Type General Article