UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31446

10.1 EDK, ppc440mc_ddr2 - How do I use the ppc440mc_ddr2 signal MI_MCCLKDIV2?

Description

What is the signal MI_MCCLKDIV2? Which clock is divided to produce it?

Solution

MI_MCCLKDIV2 is the divided-by-2 version of MI_MCCLK. 

 

The data sheet is updated starting with EDK 10.1, Service Pack 3.

AR# 31446
Date Created 08/13/2008
Last Updated 05/23/2014
Status Archive
Type General Article