When simulating the ppc440mc_ddr2 core, I find that calibration does not finish. How do I resolve this issue?
This problem might be caused by a behavioral delay on an instantiated flip-flop in the ppc440mc_ddr2 code. Delaying CLKDV by at least 100 ps from CLK might resolve the issue.
This issue is planned to be fixed in the newest version of ppc440mc_ddr2 released with EDK 11.2.