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AR# 31450

10.1 EDK, ppc440mc_ddr2 - Calibration hangs in stage 3 during simulation


When simulating the ppc440mc_ddr2 core, I find that calibration does not finish. How do I resolve this issue?


This problem might be caused by a behavioral delay on an instantiated flip-flop in the ppc440mc_ddr2 code. Delaying CLKDV by at least 100 ps from CLK might resolve the issue. 


This issue is planned to be fixed in the newest version of ppc440mc_ddr2 released with EDK 11.2.

AR# 31450
Date 05/23/2014
Status Archive
Type General Article
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