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AR# 31455 11.2 System Generator for DSP - When I use the CIC Compiler filter with an input data rate less than the system clock rate controlled by ND, I see mismatches between the simulation results in System Generator vs. hardware co-simulation

Description

Keywords: SysGen, post-translate, post-map, ND, CE, sample rate

When I use the CIC Compiler filter, I see mismatches between the simulation results in System Generator versus hardware co-simulation, or post-PAR simulation when I gate the input with the ND control signal. If ND is always held High, the results are the same in behavioral simulation, post-PAR, and hardware.

Solution

This is due to a known issue with the CIC Compiler. The ND and CE signals do not operate properly to gate the input to the core.

For further details on this issue, see (Xilinx Answer 31456).

This issue is resolved in 11.3 with the latest version of the CIC Compiler v1.3.

Actions

AR# 31455
Date Created 08/14/2008
Last Updated 09/10/2009
Status Active
Type
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