LogiCORE IP Cascaded Integrator Comb Compiler (CIC Compiler) v1.2 - Why do I see different behavior in post-PAR simulation compared to behavioral? Why do I receive incorrect results when I gate my input sample rate with the ND and CE signals?
Description
Keywords: CIC, post-translate, SysGen, post-MAP, ND, CE, sample rate
If my design uses CE or ND to control the input sample rate to the CIC Compiler, when I run a post-translate or post-PAR simulation of my CIC Compiler design, the results are different than my behavioral simulation and appear incorrect.
Solution
This could be due to a known issue with the CIC compiler core behavioral simulation model and core netlist.The behavioral simulation model does not properly model the latency through the core. The results come out of the core at a later time in post-translate simulations.
Further, if you are using ND and/or CE to gate your input data, you will see incorrect results at the output of the CIC Compiler. There is a known issue when data input to the CIC Compiler is gated with these signals. This issue appears to predominately affect multi-channel implementations.
To work around these issues, it is recommended that you slow your clock down (perhaps with a DCM) to a rate such that you can input data to the CIC on every clock cycle for decimation filters or every clock cycle for which RFD is High for interpolation filters, and hold the control signals ND and CE High.
If you are using System Generator for DSP, see (Xilinx Answer 31455).
This issue is resolved in 11.3 with the latest version of the CIC Compiler v1.3.