We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31461

10.1 Virtex-5 PAR - Clock placer might miscalculate the clock region used by EMAC and PPC components


My design contains PPC and EMAC components, and PAR is unable to route one of the global clocks in the design. What is wrong with the design?


In Virtex-5 designs that contains more than ten global clocks, the "clock placer" algorithm area constrains the global clock domains to ensure that no clock region contains more than ten clock domains. A problem has been found where the clock placer sometimes miscalculates the clock region used by PPC and EMAC clock pins. This miscalculation can lead to a situation where more than ten clock domains are placed in a clock region. One of the global clocks in that region will fail to route, not necessarily the clock with PPC and EMAC clock connections. 


This problem has been fixed in the latest 10.1 Service Pack, available at: 

The first service pack containing the fix is 10.1 Service Pack 1.

AR# 31461
Date 05/23/2014
Status Archive
Type General Article
Page Bookmarked