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AR# 31463

10.1 Virtex-5 PAR - Placer does not place PLL and related DCM in the same tile

Description

My design fails to route successfully, and PAR prints the following warning message. The problem appears to be due to bad PLL and DCM placement. Is this a known problem?

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish

the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement

or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list

of (up to 10) such unroutable connections:

Unroutable signal: INST_PLL_ADV/CLKOUTDCM0_CLKIN pin: INST_PLL_ADV/DCM_ADV_INST/CLKIN

Solution

Problems have been seen where PLL and their related DCM components are not placed together in the same tile and are unable to use the dedicated routing resources required. This problem can be avoided by locking both the PLL and DCM to appropriate sites. FPGA Editor can be used on the partially routed design to analyze the problem area and choose suitable sites.

This problem has been fixed in the latest 10.1 Service Pack, available at:

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 10.1 Service Pack 1.

AR# 31463
Date Created 08/15/2008
Last Updated 12/15/2012
Status Active
Type General Article