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AR# 31510

LogiCORE Divider Generator v2.0 - Why does my output have a rounding error when using signed inputs?


Why does my output have a rounding error when using signed inputs? That is, the LogiCORE Divider Generator v2.0 has a rounding bug when I use it in signed inputs.

4/3 gives a fractional of 10 (thus the correct .3125).

4/-3 gives a fractional of -11 (thus the incorrect .34375).


This problem is solved in the Divider Generator v3.0.

You can work around this problem by generating an core with unsigned inputs and generating the sign bit yourself. Following is an example in VHDL.

Example core instantiation:

-- component instantiation 

DUT: div_gen_v2_0 port map ( clk => clk, ce => ce, dividend => dividend, divisor => divisor, quotient => quotient, fractional => remainder, rfd => rfd);

To generate the sign-bit yourself, you need to make these changes:

  1. Add the following VHDL packages:
    use IEEE.math_real.all;
    use ieee.std_logic_signed.all;
  2. Add this additional code to your design:
    signal pipe : std_logic_vector(17 downto 0); 
    signal unsigned_dividend : std_logic_VECTOR(4 downto 0); 
    signal unsigned_divisor : std_logic_VECTOR(4 downto 0); 
    signal unsigned_quotient : std_logic_VECTOR(4 downto 0); 
    signal unsigned_remainder : std_logic_VECTOR(5 downto 0); 


    unsigned_dividend <= ABS(dividend); 
    unsigned_divisor <= ABS(divisor); 

    -- component instantiation 
    DUT: div_gen_v2_0 
    port map ( 
    clk => clk, 
    ce => ce, 
    dividend => unsigned_dividend, 
    divisor => unsigned_divisor, 
    quotient => unsigned_quotient, 
    fractional => unsigned_remainder, 
    rfd => rfd); 

    -- pipe for sign 
    SignPipe_Proc: process(clk) 
    if (falling_edge(clk)) then 
    pipe(17) <= dividend(4) XOR divisor(4); 
    for i in 17-1 downto 0 loop 
    pipe(i) <= pipe(i+1); 
    end loop; 
    end if; 
    end process SignPipe_Proc; 

    Signing_Proc: process(clk) 
    if (rising_edge(clk)) then 
    if pipe(0) = '1' then 
    quotient <= (NOT unsigned_quotient) + 1; 
    quotient <= unsigned_quotient; 
    end if; 

    -- do nothing with remainder 
    remainder <= unsigned_remainder; 
    end if; 
    end process Signing_Proc;


For a detailed list of LogiCORE Divider Generator Release Notes and Known Issues, see (Xilinx Answer 29120).

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
29120 LogiCORE IP Divider Generator - Release Notes and Known Issues N/A N/A
AR# 31510
Date 12/03/2013
Status Active
Type General Article
  • Divider