UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31512

LogiCORE Ethernet AVB Endpoint v1.1 - Release Notes and Known Issues for ISE 10.1 IP Update 3 (IP_10.1.3)

Description

This Answer Record contains the Release Notes for the LogiCORE Ethernet AVB Endpoint v1.1, which was released in ISE 10.1 IP Update 3 and includes the following: 

 

- General Information 

- New Features  

- Bug Fixes  

- Known Issues  

 

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

General Information 

 

- This is the initial release of the Ethernet AVB Endpoint Core.  

 

The following are Generated out of CORE Generator: 

- Ethernet AVB Endpoint core netlist 

- Example design HDL top-level and associated HDL files 

- Demonstration test bench to exercise the example design 

- Documentation Directory containing Data Sheet, Getting Started Guide, and Users Guide 

 

Known Issues 

 

1) For Spartan-3A DSP, the core contains an incorrect clock enable in the 8 KHz clock derivation logic. This is fixed in the below patch. 

 

 

2) MAC Header Filter issues: 

 

The Broadcast Address recognition logic has a pipeline delay bug: the 1st 5 bytes of the MAC DA are correctly identified. However, an error in the 6th byte incorrectly causes a Broadcast Address to be signaled. This is fixed in the below patch. 

 

A similar issue exists for the eight configurable MAC Header Filters. These are capable of recognizing the bit pattern of the first 16 bytes in a received frame. Like the Broadcast recognition bug, a bit error in the last byte of this check (the 16th byte in this case) could slip through unnoticed, resulting in a false filter match. This is fixed in the below patch.  

 

3) The core is not compliant with the P802.1AS specification. PTP packets are incorrectly identified using the Destination Address; they should be identified using the Length/Type field. This is fixed in the below patch.  

 

4) Out of date resource utilization figures were used in the Datasheet. This is fixed in the below patch. 

 

Patch 

To resolve issues 1 through 4 from the list of issues above, apply the following patch to the Xilinx ISE installation with the 10.1i Service Pack 3, IPUpdate 3: 

 

http://www.xilinx.com/txpatches/pub/swhelp/coregen/ethernet_avb_endpoint_v1_1_rev1.zip
http://www.xilinx.com/txpatches/pub/swhelp/coregen/ethernet_avb_endpoint_v1_1_rev1.tar.gz
 

1. Install the patch by extracting the contents of the ".zip" or "tar.gz" archive to the root directory of the Xilinx ISE installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.  

 

PC 

Determine the Xilinx ISE installation directory by entering the following at the command prompt: 

echo %XILINX% 

 

UNIX or Linux 

Determine the Xilinx ISE installation directory by entering the following: 

echo $XILINX 

 

NOTE: You might be required to have system administrator privileges to install the patch.  

 

2. After installing the patch, regenerate the Ethernet AVB Endpoint Core in CORE Generator. The core and supporting files produced will contain the updates mentioned above.

AR# 31512
Date Created 09/15/2008
Last Updated 05/21/2014
Status Archive
Type General Article