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AR# 31517

Virtex-5 GTP RocketIO Wizard v1.10 - Release Notes and Known Issues

Description

This Release Notes and Known Issues Answer Record is for the Virtex-5 GTP RocketIO Wizard v1.10 and contains the following information:

- New Features

- Bug Fixes

- Known Issues

Solution

1. INTRODUCTION

For the most recent updates to the IP installation instructions for this core, please go to:

http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:

http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx Virtex-5 FPGA GTP Transceiver Wizard v1.10. For the latest core updates, see the product page at:

http://www.xilinx.com/products/ipcenter/V5_RocketIO_Wizard.htm

2. NEW FEATURES

- Supports ISE 11.2

- New directory structure for the generated example design. Please refer to the Getting Started Guide (UG188) for additional information

3. KNOWN ISSUES

The following are known issues for v1.10 of this core at time of release:

- If you set the comma alignment smaller than the datapath width, incoming data can be aligned to multiple positions. The example design does not account for this, and may indicate errors even though data is being received correctly.

- In the case of Clock correction, the GTP wrapper in the Example design is configured correctly, but the BRAM data does not have embedded Clock-correction characters.

- In ES silicon, the logic added to make TX timing more reliable, timing closure at fabric rates of 312.5 MHz and higher may require significant effort. For best results, use a 16 or 20-bit interface for line rates higher than 1.25 Gbps.

- RX buffer bypass in Oversampling mode is not supported.

- When using RXRECCLK to generate RXUSRCLK/2, it is possible that the design will not meet timing. Please refer to AR 32996 for more information

- RST not held for 3 CLKIN cycles simulation warning. Please see AR 32230 for more information.

- May observe X's and timing simulation failures when doing back annotated simulation when using either the tx_sync deskew module or the fabric clock correction module.

The most recent information, including known issues, workarounds, and resolutions for this version is provided in the release notes Answer Record for the ISE 11.2 IP Update at

http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

4. TECHNICAL SUPPORT

To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

5. CORE RELEASE HISTORY

Date By Version Description

===============================================================================

06/24/2009 Xilinx, Inc. 1.10 ISE 11.2 Release

06/27/2008 Xilinx, Inc. 1.9 TX Phase Alignment updates

03/24/2008 Xilinx, Inc. 1.8 ISim, IPProtect, SRIO, SX240T support

10/10/2007 Xilinx, Inc. 1.7 Extended lxt package support

08/15/2007 Xilinx, Inc. 1.6 9.2i support

05/17/2007 Xilinx, Inc. 1.5 CPRI and OBSAI support

03/01/2007 Xilinx, Inc. 1.4 Extensive new features

11/30/2006 Xilinx, Inc. 1.3 Bug fixes

10/10/2006 Xilinx, Inc. 1.2 Initial release

===============================================================================

AR# 31517
Date Created 06/24/2009
Last Updated 12/15/2012
Status Active
Type General Article