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AR# 31518

Virtex-5 FPGA GTX RocketIO Wizard v1.5 - Release Notes and Known Issues for ISE Software 10.1 IP Update 3 (IP_10.1.3)


This Release Notes and Known Issues Answer Record is for the Virtex-5 FPGA GTX RocketIO Wizard v1.5 and contains the following information:

- New Features

- Known Issues



- Support for the new TXT Family (TX150T-1156/1759, TX240T-1759) - TXT devices have two columns of Tiles, left column and right column. When a TXT device is selected in the CORE Generator project options, Page 1 of the Wizard shows a Tile Column selection box with 'left' and 'right' choices. Only one column can be selected at a time. If a design uses Tiles from both columns, run the Wizard twice, once with right column selection and once with left column selection. Merge these two designs.

NOTE: On Tile coordinates, in TXT devices, the left column has the X0 indices, and the right column has the X1 indices. In FXT devices, there is only one column on the right with X0 indices. This difference should be noted when porting designs from the FXT to the TXT family.

- TX Phase Alignment Updates - New radio button for "Lane-to-lane deskew" mode on Page 4 of the Wizard under TX PCS/PMA Alignment. Select this mode if your application needs to minimize Lane-to-lane TX Skew using the TX Phase Alignment circuit. In this mode, the Wizard outputs a new TX_SYNC module that implements the Phase Alignment procedure described in UG198 Section 1, Chapter 6 - "TX Buffering, Phase Alignment, and TX Skew Reduction".

The Wizard generates a TX_SYNC module for each tile selected. This module performs Phase Alignment for both GTX0 and GTX1 in a tile. This implies a restriction that "Lane-to-lane deskew" mode must be selected on both GTX0 and GTX1, unless one of them in unused. "Lane-to-lane deskew" mode on one GTX and "Enable TX Buffer" or "Bypass TX Buffer" mode on the other GTX is not supported.

The Phase Alignment procedure involves DRP operations on the attributes TX_XCLK_SEL0/1. The TX_SYNC module provides an interface for User DRP operations. User DRP operations are blocked when the module is accessing DRP for Phase Alignment related operations.

NOTE: TX Buffer Bypass is an advanced feature and is not recommended for normal operation.


- For some of the designs, timing closure at fabric rates of 312.5 MHz and higher might require significant effort. For best results, use a 16/20/32/40 bit interface for line rates higher than 2.5 Gbps.

- When migrating designs from version 1.5 of the Wizard from 10.1 to 11.x, the newest Wizard will need to be used. Rerunning v1.5 in the 11.1 tools is not supported.

The most recent information, including known issues, work-arounds, and resolutions for this version, is provided in the release notes Answer Record for the ISE 10.1 IP Update at:


AR# 31518
Date Created 10/06/2008
Last Updated 12/15/2012
Status Active
Type General Article