We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 31519: Virtex-4 RocketIO Wizard v1.7 - Release Notes and Known Issues for ISE 10.1 IP Update 3 (IP_10.1.3)
Virtex-4 RocketIO Wizard v1.7 - Release Notes and Known Issues for ISE 10.1 IP Update 3 (IP_10.1.3)
This answer record contains the release notes for the Virtex-4 RocketIO Wizard v1.7 released with 10.1 IP Update 3.
ISE 10.1 software support.
A silicon version file for Production Step 1 was added.
Possible Reset glitch coming out of Wizard - From compile to compile, some channels work reliably, and some channels do not. These failing channels persist in failing even if the device is reconfigured, power-cycled, or reset.
CR 451281: Registered PMA_RESET, PCS_RESET, READY outputs from the init block.
Need to add special reset consideration to GT11_INIT_TX for 8-byte mode - The Wizard clocks this signal on USRCLK, which means that there is only a 50% chance of the Wizard design being in spec from startup to startup.
CR 455324: Added a TXUSRCLK2 negative edge flop on the TXRESET output; no action required for the RX side.
The following are known issues for version 1.6 of this core at time of release:
The GT11 smartmodel will produce RX Disparity errors due to rounding problems for some reference clock periods. If, in simulation, the MGTwrapper locks successfully, but shows numerous disparity errors, edit testbench/example_tb.v(hd) and increment or decrement the REFCLK period by 0.01. This is the case for Fiber Channel 2x and 4x, for example, where the refclk period must be changed from 4.71 ns to 4.7 ns.
OOB signaling is not supported in simulation.
The example design does not currently include blocks to demonstrate Channel Bonding and Clock Correction.
Setting the comma alignment (Wizard page 4) smaller than the data path width allows incoming data to be aligned to multiple positions. The example design does not account for this and might indicate errors even though data is being received correctly.
The example designs provide little support for CRC. The wrapper will configure the CRC blocks, but additional work is required to test and connect the logic.
Be careful to use run lengths supported by your silicon version when selecting the 'no encoding'/'no decoding' on Wizard page 3.
Example designs for configurations using different data widths for TX and RX might not function.
Configurations using different line rates for TX and RX on the same MGT have not been thoroughly tested, and might not work.
Wizard page 2 (Placement Customization) allowed selection of unbonded MGTs on the xc4vfx60 in the ff672 package. MGTs X0Y0, X0Y1, X1Y0, and X1Y1 are not connected to external pins.
Multilane protocol files such as XAUI might not turn on all required MGTs in some packages. If your wrapper is missing lanes, please recustomize your wrapper and select the needed MGTs on Wizard page 2.
64B/66B options have not been tested in hardware. Devices supporting 64B/66B were not available at development time.
Was this Answer Record helpful?
Virtex-4 RocketIO Transceiver Wizard