We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31532

10.1 EDK SP3, plbv46_pcie v3.00.a - The latest "plbv46_pcie v3.00.a" core fixes many issues with PLBv46_PCIe bridge versions v1.00.a, v2.00.a, v2.01.a and v2.01.b


PLBv46_PCIe bridge versions v1.00.a, v2.00.a, v2.01.a and v2.01.b are not supported in EDK 10.1.3 and new EDK versions due to changes in the PCIe GTX primitive that is instantiated in the PCIe hardcore wrapper. The wrapper with the obsoleted GTX primitive is utilized in the PCIe bridge versions v1.00.a, v2.00.a, v2.01.a and v2.01.b. PLBv46_PCIe bridge version v3.00.a instantiates the new GTX primitive and must be used in EDK 10.1.3 and newer EDK versions. Note that v3.00.a is available in EDK 10.1.3 and newer releases. Shown below are the changes in the PLBv46_PCIe bridge core in revisioning from v2.01.a to v3.00.a. Please note that 1 generic was removed and 1 generics was added. In addition, 1 input and 2 output signals were removed. Furthermore, the number of lanes is restricted to x1 only in this first release. EDK 11.1.0 will release v3.00.b which supports x1, x4, and x8 lanes.

Acronym below: "CR" refers to Change Request and "IR" refers to internal Issue Request.

10.1.3 - Changes in VHDL sources (.vhd)



v3.00.a contains the LogiCORE IP Endpoint Block Plus v1.8 for PCI Express proprietary IP and the EDK pcores for v3.00.a is encrypted to secure the Block Plus core. All v3.00.a bridge code with the exception of the Block Plus core is available in hdl format and can be obtained by accessing Answer Record #31431.

v3.00.a is based on v2.01.a and has the following updates

1. Number of PCIe Lanes reduced in this first release to x1 only
2. C_DEVICE_TYPE generic was removed
3. C_SUBFAMILY generic was added
4. GTPRESET input removed
5. PCIE_USER_CLK output removed
6. PCIE_PLL_LOCK output removed
7. PCIe Block wrapper upgraded to PCIe v1.8 Block Plus wrapper
8. Bridge uses asynchronous clocking (independent PLB and PCIe core clocks)
9. New reset scheme using LinkUp output from PCIe core for reset to AUX port on proc_sys_reset module. LinkUp output added to bridge ports.

XMD configuration command "debugconfig -reset_on_run system disable" is required to download elf-file with XMD when new reset scheme is used. This configuration command eliminates reset on elf-file download. If it is not configured with this option, then the pcie will be reset on download, which makes the link go down, and will put the processor in reset and stop the elf-file download.

10. GTX(P) configuration parameter settings for voltage swing and preemphasis changed

11. IR476854 Assertion of PLB_Rst when the PCIe link is up will cause the Endpoint bridge to issue malformed TS1 ordered sets during retraining.

The link does recover after this anomaly.

12. IR476855 When RC initiates a hot reset to the Endpoint bridge the bridge generates reserved 8b/10b symbols. The link does recover after this anomaly.

13. IR477035 When RC initiates a hot reset to the Endpoint bridge the bridge generates malformed SKIP ordered set. The link does recover after this anomaly.

14. BP wrapper module for credit fifo is upgraded to v1.9 version

15. Parameter C_CALENDAR definition changed to match BP v1.8 construct


The latest core in the EDK 10.1 Service Pack 3 fixes many issues documented in the Change Log.

Please use the latest "plbv46_pcie v3.00.a" in the EDK 10.1 Service pack 3.
AR# 31532
Date 08/27/2010
Status Active
Type General Article
  • EDK - 10.1 sp2
  • EDK - 10.1
  • EDK - 10.1 sp1
  • PLBv46 PCIe
Page Bookmarked