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AR# 31556

LogiCORE Block Memory Generator v2.8 - Release Notes and Known Issues for ISE 10.1 IP Update 3 (10.1_IP3)

Description

Keywords: CORE, Generator, ip3_k, mem, memory, asynch, asymmetric, nonsymmetric, non-symmetric, block RAM, RAMB, block RAM, BRAM, RAMB16, RAMB, simulation, UniSim, SimPrim, unisims, simprims, NetGen, SDF

This Release Notes and Known Issues Answer Record is for the Block Memory Generator v2.8 released in ISE 10.1 IP Update 3 and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information
The Xilinx Block Memory Generator v2.8 LogiCORE should be used in all new Virtex-5, Virtex-4, Virtex-II, Virtex-II Pro, Spartan-II/E and Spartan-3 /-3E /-3E XA /-3A /-3 XA designs wherever a block memory is required. This core supersedes the Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores, but is not a direct drop-in replacement. A Block Memory Migration Kit is available on Xilinx.com to convert Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores to the newer Block Memory Generator Core format.

Please see the Block Memory Core Migration Kit available at:
http://www.xilinx.com/ipcenter/blk_mem_gen/blk_mem_gen_migration_kit.htm

Also, see (Xilinx Answer 24848) for known issues of the migration kit, and (Xilinx Answer 29168) for changes made from pre-v2.4 XCO parameters.

A new CORE Generator feature is available to upgrade the Block Memory Generator from v2.4 to the latest core. This feature is part of CORE Generator, and it is visible only if you open an existing CORE Generator project with a previously generated Block Memory Generator v2.4 core. See the "Upgrading a Core" section of the CORE Generator User Guide (Software Manuals).

(Xilinx Answer 24712) How to test user logic that triggers ECC SBITERR and DBITERR outputs in the Block Memory Generator
(Xilinx Answer 31378) BitGen DRC Warnings Are Produced When DOA is Unused and DIA is Tied to Ground
(Xilinx Answer 31377) "ERROR:ip - build_algo_return: For the configured RAM size, the number of block RAMs used exceeds the maximum number of block RAMs in all available architectures (550)?


New Features in v2.8
- Virtex-5 TXT support
- New Low Power implementation option to reduce power consumption by the core
- Customization GUI now reports the exact size of the MUX used for pipelining for all algorithms


Resolved Issues in v2.8
- Power utilization the same for single port configurations and dual port configurations of the core. (In previous versions of the core, Port B was always enabled by default. Hence, single port configurations resulted in the same power utilization as dual port configurations. This has now been changed and Port B is disabled in single port configurations.) - CR 430719

- The customization GUI for the v2.7 core does not display the ECC option for Virtex-5 single port RAM configurations. - CR 468611

(Xilinx Answer 30401) Block Memory Generator GUI crashes when certain ranges of Write Depth and Write Width values are
selected - CR 433002

- Block Memory Generator resource utilization for single port configurations is double that of the legacy single port Block Memory core for Spartan-3 and Virtex-II derivative families. (The extra wide 256x72 primitive available for single port configurations was not being implemented for Spartan-3 and Virtex-II derivative families.) - CR 469821


Known Issues in v2.8

(Xilinx Answer 32290) READ_FIRST mode does not work in Virtex-5 Single Port ECC configurations

(Xilinx Answer 32037) CORE Generator GUI displays the incorrect latency for an ECC enabled core

(Xilinx Answer 24034) Core does not generate for large memories
The maximum size of the memory that can be generated varies depending on the machine the CORE Generator is run on. For example, a Dual Pentium-4 server running at 3.6GHz with two Gig RAM can generate a memory core that is 1.8 MBits or 230 K Bytes. - CR 415768

(Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUT bus


Device Issues
The Virtex-4 and Virtex-5 Errata is located at:
http://www.xilinx.com/support/mysupport.htm
The Block Memory Generator Core is subject to all block RAM issues listed in the Errata.

Block Memory Generator v2.7 Known Issues
-The Block Memory Generator v2.7 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.7 issues, see (Xilinx Answer 30055).

Block Memory Generator v2.6 Known Issues
-The Block Memory Generator v2.6 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.6 issues, see (Xilinx Answer 29247).

Block Memory Generator v2.5 Known Issues
-The Block Memory Generator v2.5 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.5 issues, see (Xilinx Answer 25459).

Block Memory Generator v2.4 Known Issues
-The Block Memory Generator v2.4 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.4 issues, see (Xilinx Answer 24555).

Block Memory Generator v2.3 Known Issues
-The Block Memory Generator v2.3 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.3 issues, see (Xilinx Answer 24229).

Block Memory Generator v2.2 Known Issues
-The Block Memory Generator v2.2 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.2 issues, see (Xilinx Answer 23849).


Revision History
09/19/2008 - Initial Release
01/16/2009 - Added AR 32037 to known issues
03/25/2009 - Added AR 32290 to known issues
AR# 31556
Date Created 09/04/2008
Last Updated 03/26/2009
Status Active
Type General Article