This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target for PCI-X v5.166 released in ISE 10.1 IP Update 3 and contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
The LogiCORE PCI v5.166 supports Virtex-4, Virtex-II Pro, and Virtex-E architectures only. For Virtex-5 devices, use the v6.8 PCI-X Core. For more information on this core, refer to (Xilinx Answer 31570).
-ISE 10.1sp3 Support
-The release notes text file generated with the core lists a known issue regarding CR 447306. This issue was fixed in v5.165. See (Xilinx Answer 30118). The release notes text file mistakenly lists this as a known issue.
-With newer versions of ModelSim, when running the example simulation it might be necessary to add this option to the vsim command:
vsim -voptargs="+acc" -L unisims_ver -t ps work.TEST_TB glbl
This argument instructs ModelSim not to optimize internal signals in the simulation model.
06/17/2009 - Added MTI note on vsim command.
09/19/2008 - Initial Release.