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AR# 31572

Endpoint Block Plus Wrapper v1.9, v1.9.1, v1.9.2, v1.9.3, and v1.9.4 for PCI Express - Release Notes and Known Issues for ISE 10.1 IP Update 3 (IP_10.1.3)

Description


This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.9, released in ISE 10.1 IP Update 3, and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution


General Information

The LogiCORE Endpoint Block Plus for PCI Express requires a license to generate and implement the core. There is no charge for this license.

To obtain the license, visit the product lounge at:
http://www.xilinx.com/products/ipcenter/V5_PCI_Express_Block_Plus.htm

Important Note:
There is a v1.9.4 patch available in (Xilinx Answer 30124). This patch fixes issues listed below as (Xilinx Answer 31635), (Xilinx Answer 31776), (Xilinx Answer 31845), (Xilinx Answer 31844), (Xilinx Answer 32031), (Xilinx Answer 32170), (Xilinx Answer 32171), and (Xilinx Answer 32276).

Important Note:
The Expansion ROM BAR is always enabled in the integrated block. The v1.6.1, v1.7.1, and v1.8 Endpoint Block Plus Core had a work-around that disabled the Expansion ROM BAR, since most applications do not make use of it. However, this work-around caused data corruption on incoming packets; see (Xilinx Answer 31164). The best solution to this problem was to remove the work-around causing the Expansion ROM to once again be enabled. You should review Chapter 3 (page 43) of the LogiCORE IP Endpoint Block Plus v1.9 for PCI User Guide (UG341):
http://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf

New Features

- ISE 10.1 SP3 software support
- Added support for Virtex-5 FPGA TX150T and TX240T
- Added support for ISE Project Navigator Flow
- Added support for Expansion ROM BAR

Resolved Issues

CR 473951- Enabled Expansion ROM BAR
Removed workaround to disable Expansion ROM BAR, as this was causing data corruption with certain traffic patterns. This feature is now permanently enabled and cannot be disabled. Users will need to respond to accesses to this BAR. Please refer to the Endpoint Block Plus v1.9 for PCI Express User Guide, Chapter 3, section on Base Address Registers for further details.

CR 476758 - TX lockup due to SRL 16E power on initialization issue
Issue resolved where the Transmit path of the core locks up due to a Power On Initialization Issue with the SRL 16E Calendar logic.

CR 471589 - Update GTX wrapper
Update the GTX wrapper to remove TXBUFFERBYPASS mode.

CR 476757 - TX lockup due to link partner advertising infinite data credits
Issue resolved where a link partner advertising infinite data credits caused the transmit path of the core to lock up.

CR 472508 - Unexpected deassertion of trn_tdst_rdy_n in response to trn_tsrc_rdy_n deassertion
Issue resolved where deassertion of trn_tsrc_rdy_n causes trn_tdst_rdy_n deassertion.

CR 472342 - Set Slot Clock bit in Link Status Register set incorrectly
Selecting the Slot Clock Configuration option in the GUI does not set the Set Slot Clock bit in the Link Status Register.

CR 474746 - GUI Issue with Bar 3 configuration
Issue resolved with GUI for Bar 3 configuration. When Bar 3 was selected for customization, the fields were not enabled for customization.

CR 437528 - GUI allowing 32-bit BAR to be set as Pre-fetchable
Issue resolved where the GUI was allowing a BAR set as 32-bit BAR to also be set as Pre-fetchable.

CR 473935- System Verilog compatibility
Updated user application (pci_exp_usrapp_com.v) to be System Verilog compatible.

CR 472801 - False failure reporting in PIO tests resolved
PIO tests fixed to resolve false failure reporting. These tests were passing; however, a failure was reported.

CR 474892 - Data Corruption in example design test for 4-lane endpoint on FX70T
Data corruption issue resolved in example design test for a 4-lane endpoint on FX70T.

CR 476165 - Extra feedback BUFG removed from PLL clocking network
Removed extra feedback BUFG from the PLL clocking network. This BUFG is redundant because the user clock in the core does not need to be edge-aligned to the reference clock input.

CR 438737 - License Check Failure Warning issued while generating a core from CORE Generator
Issue resolved where a Warning was being issued while generating the core from CORE Generator for a License Check failure.

Known Issues

There are three main components to the Endpoint Block Plus Wrapper for PCI Express:

- Virtex-5 FPGA Integrated Block for PCI Express
- Virtex-5 FPGA GTP/GTX Transceivers
- Block Plus Wrapper FPGA fabric logic

The known issues for the integrated block and GTP/GTX transceivers are found in the Block Plus core user guide :
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_v5pciexpressblockplus.htm

Block Plus Wrapper FPGA fabric logic

(Xilinx Answer 31210) Endpoint Block Plus Wrapper for PCI Express v1.9 - Interrupt Status bit not set when generating Legacy Interrupt

(Xilinx Answer 31211) Endpoint Block Plus Wrapper v1.9 for PCI Express - Link transitioning to L0s causes BAR settings to reset

(Xilinx Answer 31460) Endpoint Block Plus Wrapper v1.9 for PCI Express - CORE Generator Customization GUI, Page 7 TXPREEMPHASIS wrong for FXT

(Xilinx Answer 31635) Endpoint Block Plus Wrapper v1.9 for PCI Express - Fails to link train in Gen 2 Motherboard when receiver polarity reversed. Fixed in v1.9.1, see (Xilinx Answer 30124)

(Xilinx Answer 31646) Endpoint Block Plus Wrapper v1.9 for PCI Express - Dual Core UCF problems

(Xilinx Answer 31647) Endpoint Block Plus Wrapper v1.9 for PCI Express - Dual core implement_dual.bat missing

(Xilinx Answer 31649) Endpoint Block Plus Wrapper v1.9 for PCI Express - turn_off_upper_lanes Perl Script Incorrect for GTX (FXT/TXT)

(Xilinx Answer 31704) Endpoint Block Plus Wrapper v1.9 for PCI Express - Importing a v1.8 XCO to v1.9 causes Error:sim228 -An Invalid core configuration has been detected during Customization

(Xilinx Answer 31776) Endpoint Block Plus Wrapper v1.9 for PCI Express - On a lane reversed x8 link, back to back ACK issue causes TX lock up. Fixed in v1.9.1, see (Xilinx Answer 30124).

(Xilinx Answer 31843) Endpoint Block Plus Wrapper v1.9 for PCI Express - Power management transition from D0 to D3hot to D0 can cause transmit stall

(Xilinx Answer 31844) Endpoint Block Plus Wrapper v1.9 for PCI Express - TLP with TLP Digest (ECRC) attached dropped in RX path of wrapper. Fixed in v1.9.1, see (Xilinx Answer 30124)

(Xilinx Answer 31845) Endpoint Block Plus Wrapper v1.9 for PCI Express - Endpoint completely fails to train and does not transfer any TS ordered sets. Fixed in v1.9.1, see (Xilinx Answer 30124)

(Xilinx Answer 31850) Endpoint Block Plus Wrapper v1.9 for PCI Express - Simulation testbench writes to incorrect address for device control register

(Xilinx Answer 31851) Endpoint Block Plus Wrapper v1.9 for PCI Express - PIO design file PCI_EP_MEM_ACCESS.vhd corrupts block RAM data when checking byte enables

(Xilinx Answer 32031) Endpoint Block Plus Wrapper v1.9.1 for PCI Express - Training time increased in simulation

(Xilinx Answer 32077) Endpoint Block Plus v1.9 - Cannot generate core for the XC5VTX150T-FF1156

(Xilinx Answer 32091) Endpoint Block Plus Wrapper v1.9 for PCI Express - Downstream Port model drops completions with length 64 bytes and greater

(Xilinx Answer 32170) Endpoint Block Plus Wrapper v1.9 for PCI Express - Transmit side stalls when sending packets, causing trn_tdst_rdy_n to deassert indefinitely

(Xilinx Answer 32171) Endpoint Block Plus Wrapper v1.9 for PCI Express - Completion dropped and receiver overflow on RX interface when using completion streaming mode

(Xilinx Answer 32270) Endpoint Block Plus Wrapper v1.9 for PCI Express - Using Non-Synchronous Links with Virtex-5 FXT (GTX RocketIO) May Result in Data Errors

(Xilinx Answer 32276) Endpoint Block Plus Wrappre v1.9.3 for PCI Express - Cannot close timing with the v1.9.3 patch



Revision History
09/22/2009 - Removed reference to UG493 and replaced with UG341
08/11/2009 - Fixed title for AR 32170
04/13/2009 - Updated title to reflect versions
03/19/2009 - Added 32276 and v1.9.4 patch
03/13/2009 - Added 32270
02/25/2009 - Added 32170, 32171, and v1.9.3 patch
02/03/2009 - Added 32091
01/27/2009 - Added 32077
01/15/2009 - Updated with v1.9.2 patch information.
01/09/2009 - Added 32031.
12/08/2008 - Updated with v1.9.1 patch information.
10/28/2008 - Added ARs 31850, and 31851.
10/27/2008 - Added ARs 31843, 31844, and 31845.
10/07/2008 - Added AR 31776.
09/19/2008 - Initial Release.
AR# 31572
Date Created 09/12/2008
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Endpoint Block Plus Wrapper for PCI Express