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AR# 31573

LogiCORE IP Serial RapidIO v5.1 - Release Notes and Known Issues for 10.1 IP Update 3 (10.1.3)


This Release Notes and Known Issues Answer Record is for the Serial RapidIO v5.1, released in 10.1 IP Update 3, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:



IMPORTANT: All users should download and install the v5.1 Rev1 patch available from the link below. This patch fixes some critical issues in v5.1. The resolved issues and known issues below reflect both the problems fixed in this patch (v5.1 Rev1), and for the base v5.1 core.


This patch requires ISE software 10.1.03 with IP Update 3.

You must take the following steps to install the Serial RapidIO Core patch:

1. Prior to installing the update, you must install the latest IP Update release required by the patch as stated above. The IP Update is available from:


2. Unzip patch ZIP archive to your Xilinx installation directory as pointed to by your XILINX path variable. The archive asks you whether to overwrite the existing files; select "Yes to All" and allow it to overwrite these files.

New Features

- Redesigned configurable LogiCORE IP Buffer Design

- Full VHDL support for Virtex-5 FPGA solutions

Resolved Issues

- (Xilinx Answer 31864) Full Hardware Evaluation core does not assert "lnk_trdy_n"

- Version fixed : v5.1 rev1

- CR#493479 - Modified initial state in evaluation cores.

- (Xilinx Answer 31834) Generation of PHY-only core fails with "HDLCompilers:87" error

- Version fixed : v5.1 rev1

- CR#493162 - Shared file between buffer and log added to buffer file list.

- (Xilinx Answer 31617) Virtex-4 FPGA core has long initialization time.

- Version fixed : v5.1 rev1

- CR#481684 - Virtex-4 FPGA initSM modified to prevent branch to silent when RX PCS resets in DISCOVERY state.

- LogIO local arbitration does not account for valid causing re-arbitration prior to legitimate packet completion.

- Version fixed : v5.1

- CR#478748 - Valid used to gate mresp_eof_n and iresp_eof_n for local arbitration.

- A ireq_dsc_n asserted for an undefined packet type is not propagated by the logical layer.

- Version fixed : v5.1

- CR#478541 - Undefined packet type decode now passes dsc to buffer, allowing packet to be dropped.

- 16-bit deviceID cores might see a maintenance response transaction presented but not validated on the IResp interface, resulting in a lost transaction by the logical layer.

- Version fixed : v5.1

- CR#474894 - Fixed issue when the maintenance response is followed immediately by a single DWord SWrite packet.

- SourceID not configurable for IReq port.

- Version fixed : v5.1

- CR#473938 - Added ireq_src_id port to logical layer. All transmit source IDs should now be configurable and all received destination IDs observable.

- Write enables into LogIO registers are not allowing partial register writes.

- Version fixed : v5.1

- CR#473441 - Write enables now implemented for all LogIO registers, allowing byte-wise writes of CSRs such as the deviceID register and BAR.

- Message response transaction received as a user defined packet type using 16-bit device IDs appears as a corrupted packet on the IResp interface.

-Version fixed : v5.1

-CR#473400, CR#473693 - Fixed LogIO RX to properly handle all user-defined types.

Known Issues in v5.1 Rev1

- (Xilinx Answer 32188) Virtex-5 FXT core may show data errors and "input-error stopped" state

- Version to be fixed: v5.3

- (Xilinx Answer 32122) Re-Transmit Suppression Support bit set incorrectly as 1'b0

- Version to be fixed: v5.2

- (Xilinx Answer 32063) Buffer layer may corrupt single-cycle RX packets

- Version to be fixed: v5.2

- (Xilinx Answer 32022) Snooper logic reports errors in simulation of x1 core

- Version to be fixed: v5.2

- (Xilinx Answer 32316) If 16-bit Device IDs are used, treq_vld_n can assert before treq_sof_n on an SWRITE

- Version to be fixed: Fix Not Scheduled

- (Xilinx Answer 31962) Virtex-II Pro Core fails timing when buffer is 32 words deep. The core is not supported in Virtex-II Pro if you select a "TX Buffer Depth," or "RX Buffer Depth" of 32 on page four of the core's customization GUI. The supported options are to select either 16 words or 8 words for the buffer depth.

- Version to be fixed: Fix Not Scheduled

- (Xilinx Answer 30023) Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT core configurations are unable to train down to x1 mode in Lane 2. Traindown in Lane 0 works successfully, but the Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT configurations are unable to Traindown in Lane 2. The RocketIO transceivers only allow Traindown to the channel bonding master. CR 457109.

- Version to be fixed: Fix Not Scheduled

- (Xilinx Answer 30021) Core reinitialization during error recovery causes recoverable protocol error. This is a corner condition that could occur if the core is forced to reinitialize (i.e., - force_reinit) while it is in the process of error recovery. If this condition occurs, packets will be sent during recovery's quiet period. This situation is recoverable. CR 457885.

- Version to be fixed: Fix Not Scheduled

- (Xilinx Answer 29522) Post-Synplicity synthesis implementation runs might exhibit UCF failures. Synplicity generated net names are not consistent with XST generated names and might not be consistent between core types. The ".ucf" file must be edited in these failure cases. CR 447782.

- Version to be fixed: Fix Not Scheduled

- (Xilinx Answer 24982) PNA cause field might occasionally reflect a reserved value. The cause field is for debug purposes only and will not affect functionality. Occurrence is rare and requires alignment of multiple control symbols. CR 436767.

- Version to be fixed: Fix Not Scheduled

(Xilinx Answer 24970) Control Symbols might be lost on reinit. This is an unusual and ultimately recoverable error. Set the "Additional Link Request Before Fatal" value on the Physical Configuration page of the GUI to "4" in order to prevent a lost Link Request or Link Response from causing the core to enter the port error state.

- Version to be fixed: Fix Not Scheduled

(Xilinx Answer 24968) Logical Rx does not support core side stalls. The Rx buffer must provide packets to the logical layer without buffer induced stall cycles. The buffer reference design provided with the core is a store and forward buffer and complies with this rule. CR 436770.

- Version to be fixed: Fix Not Scheduled

Revision History

09/19/2008 - Initial Release

10/21/2008 - Added AR 31834 to known issues

11/10/2008 - Added AR 31864 to known issues

11/11/2008 - Added FTP link for Rev1 patch and updated resolved and known issues

12/05/2008 - Added AR 31962 to known issues

01/06/2009 - Added AR 32022 to known issues

01/21/2009 - Added AR 32063 to known issues

02/12/2009 - Added AR 32122 to known issues

03/17/2009 - Added AR 32188 to known issues

03/24/2009 - Added AR 32316 to known issues

AR# 31573
Date 12/15/2012
Status Active
Type General Article
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