^

AR# 31574 10.1 Virtex-5 MAP - ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block ...

Keywords: illegal, routing, map, dcm, dcm_adv, drc

My design fails in version 10.1 with the following "illegal routing" error. This design worked okay in 9.2i, so I know my design is good. What is going wrong?

ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block
<i_srl_top/i_srl_pcix_clk_wrap/i_pci_clk_fpga/DCM_BASE_pci_clk/DCM_ADV> has CLK output pin <CLK90> with incomplete or incorrect connectivity. Routing from the <CLK90> pin to a BUFG, BUFGCTRL or PLL_ADV block type was not found. The DCM_ADV CLK output pins can only route to BUFG, BUFGCTRL or PLL_ADV block types.

This DRC error message is triggered by the presence of dangling output signals on the DCM_ADV that should have been trimmed but were not. Since the DRC check is looking for specific legal load pins on the signal, it fails when they are not detected. This specific trimming error having to do with DCM_ADV outputs has been known to occur for two different reasons:

1. "S" properties on DCM_ADV input nets are incorrectly affecting the trimming behavior of output nets. This change is related to new trimming behavior in 10.1 (Xilinx Answer 30112). It is possible to avoid this behavior by setting an environment variable that restores the old 9.2 behavior.

Windows
SET XIL_MAP_OLD_SAVE=1

Linux and Solaris
setenv XIL_MAP_OLD_SAVE 1

For general information about setting ISE environment variables, see (Xilinx Answer 11630).

2. This trimming problem has also been known to be caused by Keep Hierarchy constraints. This problem can be avoided by using the MAP option "-ignore_keep_hierarchy".

For more general information about trimming issues, see (Xilinx Answer 23990).
AR# 31574
Date Created 08/26/2008
Last Updated 08/27/2008
Status Active
Type
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