We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 31574: 10.1 to 14.7 Virtex-5 MAP - ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block ...
10.1 to 14.7 Virtex-5 MAP - ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block ...
My design fails in version 10.1 of ISE Design Suite with the following "illegal routing" error.
ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block <i_srl_top/i_srl_pcix_clk_wrap/i_pci_clk_fpga/DCM_BASE_pci_clk/DCM_ADV> has CLK output pin <CLK90> with incomplete or incorrect connectivity. Routing from the <CLK90> pin to a BUFG, BUFGCTRL or PLL_ADV block type was not found. The DCM_ADV CLK output pins can only route to BUFG, BUFGCTRL or PLL_ADV block types.
This design worked without issues in ISE 9.2i.
What is the cause of this error?
This DRC error message is triggered by the presence of dangling output signals on the DCM_ADV that should have been trimmed but were not.
Because the DRC check is looking for specific legal load pins on the signal, it fails when they are not detected.
This specific trimming error relating to DCM_ADV outputs has been known to occur for two different reasons:
"S" properties on DCM_ADV input nets can incorrectly affect the trimming behavior of output nets.
This change is related to new trimming behavior in ISE 10.1.