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AR# 31606

MIG v2.3, Virtex-5 DDR2 - Are CLK and CLK90 related?

Description

If generating the Virtex-5 DDR2 SDRAM design with the "Use DCM" option disabled (without DCM design), CLK and CLK90 are constrained as follows in the UCF:

NET "clk_0" TNM_NET = "SYS_clk_0"; 
TIMESPEC "TS_SYS_clk_0" = PERIOD "SYS_clk_0" 5 ns HIGH 50 %;
NET "clk_90" TNM_NET = "SYS_clk_90"; 
TIMESPEC "TS_SYS_clk_90" = PERIOD "SYS_clk_90" "TS_SYS_clk_0" PHASE 1.25 ns HIGH 50 %;

From these constraints, it appears the clocks are unrelated as CLK and CLK90 have an absolute period constraint.

If you generate the DDR2 SDRAM design with the "Use DCM" option enabled (with DCM design), CLK and CLK90 are considered related as the input clock of the DCM is constrained.

Solution

CLK and CLK90 need to be related clocks; thus, the constraints should be modified. This can be done by using a relative constraint and the PHASE constraint: 

NET "clk_0" TNM_NET = "SYS_clk_0";
TIMESPEC "TS_SYS_clk_0" = PERIOD "SYS_clk_0" 5 ns HIGH 50 %;
NET "clk_90" TNM_NET = "SYS_clk_90";
TIMESPEC "TS_SYS_clk_90" = PERIOD "SYS_clk_90" "TS_SYS_clk_0" PHASE 1.25 ns HIGH 50 %;

NOTE: This modification does not cause any errors during implementation.

Full details on MIG clocking structures have been added to the MIG 2.3 User Guide. The PHASE constraint is to be added in the MIG 3.0 release.

AR# 31606
Date Created 09/11/2008
Last Updated 10/09/2013
Status Active
Type General Article
Devices
  • Virtex-5
IP
  • MIG