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AR# 31610

Architecture Wizard, XtremeDSP Slice - Why does the Multiplier or Multiply Accumulate (MACC) Architecture Wizard always have a clock input, even when no registers are selected, or why is ACASCREG or MREG always set to '1' in the HDL?

Description

Why does the Multiplier or MAC Architecture Wizard always have a clock input, even when no registers are selected, or why is ACASCREG or MREG always set to '1' in the HDL? 

 

I usually notice this issue when I try to create a combinitorial DSP48, or one that does not use the 3-stage pipeline.

Solution

This is a known bug in the XtremeDSP Slice Multiply or Multiply Accumulate (MACC) Architecture Wizard output. 

 

For a list of alternative solutions to using the Architecture Wizard, see (Xilinx Answer 30101).

AR# 31610
Date Created 09/04/2008
Last Updated 05/23/2014
Status Archive
Type General Article