This issue is with BitGen, and is fixed in the 11.1 release of the design tools.
Towork around the problem, lock the RAMB18 and FIFO18 to separate locations.
UCF example:
inst "RAMB18_inst" LOC = RAMB36_X0Y1 | BEL = UPPER;
inst "FIFO18_inst" LOC = RAMB36_X0Y0 | BEL = LOWER;
You can also work around this issue by installing a patch that works with the 10.1 ISE tools.The patchis availableat the following location:
http://www.xilinx.com/txpatches/pub/utilities/fpga/ar31618.zip To use this patch, place the "virtex5.bfd" file into your "$MYXILINX/virtex5/data" or "$XILINX/virtex5/data" directory. After applying the patch, only BitGen needs to be run.
For further information on using MYXILINX, see
(Xilinx Answer 2493).
NOTE: The fix for this issue is included in the 10.1 sp3 Virtex-5 Speed File and Package Update.