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AR# 31618

Virtex-5 FPGA - RAMB18 does not function as expected when packed with FIFO18


When a RAMB18 is packed together with FIFO18, the B port of the RAMB18 does not read out the correct values. You can read the correct value with port A.


This issue is with BitGen, and is fixed in the 11.1 release of the design tools.
Towork around the problem, lock the RAMB18 and FIFO18 to separate locations.
UCF example:

inst "RAMB18_inst" LOC = RAMB36_X0Y1 | BEL = UPPER;
inst "FIFO18_inst" LOC = RAMB36_X0Y0 | BEL = LOWER;

You can also work around this issue by installing a patch that works with the 10.1 ISE tools.The patchis availableat the following location:

To use this patch, place the "virtex5.bfd" file into your "$MYXILINX/virtex5/data" or "$XILINX/virtex5/data" directory. After applying the patch, only BitGen needs to be run.
For further information on using MYXILINX, see (Xilinx Answer 2493).
NOTE: The fix for this issue is included in the 10.1 sp3 Virtex-5 Speed File and Package Update.
AR# 31618
Date 12/15/2012
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
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  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
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