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AR# 31646

Endpoint Block Plus Wrapper v1.14 for PCI Express - Dual Core UCF problems

Description

Known Issue: v1.14, v1.13, v1.12, v1.11, v1.10.1, v1.10, v1.9.4, v1.9.3, v1.9.2, v1.9.1, v1.9, v1.8, v1.7.1 

When I select the FX70TFF1136 device, CORE Generator produces an example UCF for a design using two Integrated Blocks. As described below, there are some issues with this file.

Solution

Reference Clock 

Depending on the number of blocks used or lane width selected, it might create a situation where a single input reference clock is clocking more than 7 GTX_DUALs. The ISE tools will let this pass; however, the input reference clock cannot clock more than 7 GTX_DUALs. The RocketIO GTX Transceiver User Guide, UG198 (v1.2), page 81, states the following: 

NOTE: The following rules must be observed when sharing a reference clock to ensure that jitter 

margins for high-speed designs are met: 

1. The number of GTX_DUAL tiles above the sourcing GTX_DUAL tile must not exceed three. 
2. The number of GTX_DUAL tiles below the sourcing GTX_DUAL tile must not exceed three.
3. The total number of GTX_DUAL tiles sourced by the external clock pin pair (MGTREFCLKN/MGTREFCLKP) must not exceed seven. 

To work around this, add a new reference clock input pair.  

Location Constraints 

The x8 UCF does not contain valid constraints for the second instantiation of the Endpoint Block Plus core and they are commented out. The complete UCF constraints shown below include a secondary reference clock input. Note that you will need to add the secondary clock input and IBUF to the example design instantiation of the dual core design. 

 ############################################################################### 
 # 

 # File: xilinx_dual_pci_exp_blk_plus_8_lane_ep_xc5vfx70t-ff1136-1.ucf 

 # 

 # Use this file only with the device listed below. Any other 

 # combination is invalid. Do not modify this file except in 

 # regions designated for "User" constraints. 

 # 

 # Copyright (c) 2008 Xilinx, Inc. All rights reserved. 

 # 

 ############################################################################### 

 # Define Device, Package And Speed Grade 

 ############################################################################### 

 

CONFIG PART = XC5VFX70T-FF1136-1 ; 

 

 ############################################################################### 

 # User Time Names / User Time Groups / Time Specs 

 ############################################################################### 

 

 

 ############################################################################### 

 # User Physical Constraints 

 ############################################################################### 

 

 

 ############################################################################### 

 # Pinout and Related I/O Constraints 

 ############################################################################### 

 

 # 

 # SYS reset (input) signal. The sys_reset_n signal should be 

 # obtained from the PCI Express interface if possible. For 

 # slot based form factors, a system reset signal is usually 

 # present on the connector. For cable based form factors, a 

 # system reset signal may not be available. In this case, the 

 # system reset signal must be generated locally by some form of 

 # supervisory circuit. You may change the IOSTANDARD and LOC 

 # to suit your requirements and VCCO voltage banking rules. 

 # 

 

NET "sys_reset_n" LOC = "AE13" | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ; 

 

 # 

 # SYS clock 250 MHz (input) signal. The sys_clk_p and sys_clk_n 

 # signals are the PCI Express reference clock. Virtex-5 GTP 

 # Transceiver architecture requires the use of a dedicated clock 

 # resources (FPGA input pins) associated with each GTP Transceiver Tile. 

 # To use these pins an IBUFDS primitive (refclk_ibuf) is 

 # instantiated in user's design. 

 # Please refer to the Virtex-5 GTP Transceiver User Guide 

 # (UG196) for guidelines regarding clock resource selection. 

 # 

 

NET "primary_sys_clk_p" LOC = "Y4" ; 
NET "primary_sys_clk_n" LOC = "Y3" ; 
INST "primary_refclk_ibuf" DIFF_TERM = "TRUE" ;  

NET "secondary_sys_clk_p" LOC = "D8" ;  
NET "secondary_sys_clk_n" LOC = "C8" ;  
INST "secondary_refclk_ibuf" DIFF_TERM = "TRUE" ; 

 

 # 

 # Transceiver instance placement. This constraint selects the 

 # transceivers to be used, which also dictates the pinout for the 

 # transmit and receive differential pairs. Please refer to the 

 # Virtex-5 GTP Transceiver User Guide (UG196) for more 

 # information. 

 # 

 # PCIe Lanes 0, 1 

INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTX_DUAL_X0Y3; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTX_DUAL_X0Y7; 

 

 # PCIe Lanes 2, 3 

INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTX_DUAL_X0Y2; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTX_DUAL_X0Y6; 

 

 # PCIe Lanes 4, 5 

INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" LOC = GTX_DUAL_X0Y1; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" LOC = GTX_DUAL_X0Y5; 

 

 # PCIe Lanes 6, 7 

INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" LOC = GTX_DUAL_X0Y0; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" LOC = GTX_DUAL_X0Y4; 

 # 

 # PCI Express Block placement. This constraint selects the PCI Express 

 # Block to be used. 

 # 

 

 # PCIe Lanes 0 

INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep" LOC = PCIE_X0Y0; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep" LOC = PCIE_X0Y2;  

 ############################################################################### 

 # Physical Constraints 

 ############################################################################### 

 # 

 # BlockRAM placement 

 # 

INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst" LOC = RAMB36_X4Y4 ; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst" LOC = RAMB36_X4Y28 ; 
INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X4Y3 ; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X4Y27 ; 
INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X4Y2 ; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X4Y26 ; 
INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X4Y1 ; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X4Y25 ; 
INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X4Y0 ; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X4Y24 ; 

 # 

 # Timing critical placements 

 # 

INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/tx_bridge/tx_bridge/shift_pipe1" LOC = "SLICE_X75Y16" ; 
INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available" LOC = "SLICE_X74Y6"; 
INST "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/mgmt_rdata_d1_3" LOC = "SLICE_X75Y5"; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/tx_bridge/tx_bridge/shift_pipe1" LOC = "SLICE_X75Y136" ; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available" LOC = "SLICE_X74Y126"; 
INST "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/mgmt_rdata_d1_3" LOC = "SLICE_X75Y125"; 

 ############################################################################### 

 # Timing Constraints 

 ############################################################################### 

 # 

 # Ignore timing on asynchronous signals. 

 # 

NET "sys_reset_n" TIG ; 

 # 

 # Timing requirements and related constraints. 

 # 

NET "primary_ sys_clk_c" PERIOD = 10ns; 
NET "secondary sys_clk_c" PERIOD = 10ns; 
NET "primary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out[0]" TNM_NET = "MGTCLKP" ; 
NET "secondary_ep/ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out[0]" TNM_NET = "MGTCLKS" ; 
TIMESPEC "TS_MGTCLKP" = PERIOD "MGTCLKP" 100.00 MHz HIGH 50 % ; 
TIMESPEC "TS_MGTCLKS" = PERIOD "MGTCLKS" 100.00 MHz HIGH 50 % ; 

 ############################################################################### 

 # End 

 ############################################################################### 

Revision History 

04/23/2010 - Update for ISE 12.1 and v1.14
09/16/2009- Updated for ISE 11.3 and core version v1.12. 
06/24/2009 - Updated for v1.11 and ISE 11.1 release. 
09/12/2008 - Initial Release.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35321 Endpoint Block Plus Wrapper v1.14 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 31646
Date Created 04/01/2009
Last Updated 08/26/2013
Status Active
Type Known Issues
IP
  • Endpoint Block Plus Wrapper for PCI Express