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AR# 31655

10.1 EDK - My EDK cores are not getting the correct settings for my Virtex-4 Q and Virtex-4 QR designs

Description

My EDK cores are not getting the correct settings for my Virtex-4 Q and Virtex-4 QR designs. 

 

Is there a work-around for this issue?

Solution

The following cores are affected by this problem: 

xps_ethernetlite_v2_00_b 

plbv46_pci_v1_02_a 

 

The work-around is to: 

1. Open C:\Xilinx\10.1\EDK\data\datastructure\xillib_common.tcl 

2. Modify line 206  

from: set deviceList {virtex4} 

to: set deviceList {virtex4 qvirtex4 qrvirtex4} 

3. Save and close the file. 

 

This problem is scheduled to be fixed in 11.1. 

 

For the PCI core, please refer to (Xilinx Answer 31638) for an additional patch.

AR# 31655
Date Created 09/12/2008
Last Updated 05/21/2014
Status Archive
Type General Article