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AR# 31684

ChipScope Pro, Virtex-5 IBERT - Can I use the REFCLKOUT as my IBERT system clock?


I do not have an additional clock source on my board that I can use as my IBERT system clock. How do I use the REFCLKOUT as my IBERT system clock?


NOTE: This work-around is only applicable for Virtex-5.

To use a REFCLKOUT from a GTP/GTX_DUAL instead of an external clock source, a special version of the IBERT source code is required. This special source code changes the default state of the DUALs to powered-up instead of powered-down. Additionally, the DUAL that is clocking the user logic should never be powered down during operation, or IBERT will be rendered unusable. A reconfiguration will be required to recover from that situation.

Source files:


1. Copy the ibert_v5gtp_powerup.xz and ibert_v5gtx_powerup.xz to a known location.

2. Create your IBERT core using the IBERT CORE Generator with the following differences:

- put in a dummy location for the userclk.

- put in the correct frequency for the userclk, the frequency that is *after* any DCMs/PLLs, if those components are necessary to get the frequency between 50 and 100 MHz.

3. Once the first synthesis process begins, hit the Cancel button and exit the Generator.

4. Go into the project/ibertgtp_temp or project/ibertgtx_temp directly, as applicable.

5. Edit the ibert_top.prj file so the first line points to the correct *_powerup.xz file that you placed in step 1.

6. Edit the ibert_top.v file.

- The system clock goes into the main ibert module on the DCLK_I port. We are going to change that connectivity.

- All the main clocks are actually routed to this level, using the scope_* ports. We are interested in the scope_refclkout port. This port is a bus, of the same width as the number of DUALs used in the design. The first DUAL used (smallest Y coordinate) corresponds to bit 0 of the bus.

- Change the DCLK generation section to properly connect the appropriate scope_refclkout signal to the DCLK signals. This should be either

- a BUFG on scope_refclkout[n] or

- a BUFG on scope_refclkout[n] feeding a PLL/DCM feeding a BUFG (see included example)

- Remove the DCLK_IPAD port from the top-level module

7. Edit the ibert_top.ucf file, and remove the system dclk pin location constraint.

8. run 'make -f ibert.mak'

AR# 31684
Date Created 09/18/2008
Last Updated 12/15/2012
Status Active
Type General Article