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AR# 31685

ChipScope Pro IBERT, Virtex-5 FPGA - How can I use a SYSCLK outside the 50-100 MHz range?

Description

How can I use a SYSCLK outside the 50-100 MHz range?

Solution

To use a SYSCLK outside the required range of IBERT, follow these steps:

Source Files: http://www.xilinx.com/txpatches/pub/swhelp/ise10_updates/31685.zip

1. Create your IBERT core using the IBERT CORE Generator with the following differences:
- enter the correct frequency for the userclk, the frequency that is after the DCM/PLL that is going to be added to the design as a clock multiplier or divider.
2. Once the first synthesis process begins, hit the Cancel button and exit the Generator.
3. Browse to your %XILINX%\data\chipscope directory and copy the following files to the main ibertgtp_temp project directory of your IBERT project.
- fifo_generator_v2_3_fifo_generator_v2_3_xst_1.ngc
- fifo_generator_v2_3_fifo_generator_v2_3_xst_1_blkmemdp_v6_2_xst.edn
- ibert_v5gtp_drp.xz
- ibert_v5gtp.xz
- ibert.xz
4. In the "ibertgtp_temp" directory open the "ibert_drp_wrap.prj" file and change the first line to - verilog work ibert_v5gtp_drp.xz
5. In the "ibertgtp_temp" directory open the "ibert_top.prj" file and change the first line to - verilog work ibert_v5gtp.xz
6. If using linux -In the "ibertgtp_temp" directory open the "ibert.mak" file and change the ngdbuild command to - ngdbuildintstyle silent -uc ibert_top.ucf -p 5vsx35t-3ff665 ibert_top
7. Go into the project/ibertgtp_temp or project/ibertgtx_temp directly, as applicable.
8. Edit the "ibert_top.v" file.
- The system clock goes into the main ibert module on the DCLK_I port. This connectivity is going to be changed.
- Change the DCLK generation section to add a DCM or PLL to the path, but instead of connecting an internal refclk, use the dclk. See the example attached in the linked ZIP file and below:

/*******************************************************************************

wire dclk_intermediate; -- Add this
* DCLK Generation global buffer
*/

BUFG U_DCLK_BUFG (.I(dclk_in),.O(dclk_intermediate));

PLL_ADV
#(
// Specify your clock period here in NS
.CLKIN1_PERIOD(6.6), // 150 MHz
.CLKFBOUT_MULT(4),
.DIVCLK_DIVIDE(1),

// Choose this number (integer from 1 to 128) to make sure
// the output clock is under 100 MHz

.CLKOUT0_DIVIDE(8)

) pll_refclk (
.CLKIN1(dclk_intermediate),
.CLKIN2(dclk_intermediate),
.CLKINSEL(1'b1),
.CLKFBIN(fbin),
.CLKFBOUT(fbout),
.CLKOUT0(dclk_pll),
.RST(rst),
.LOCKED(lock),
.REL(1'b0),
\.CLKOUT1(), .CLKOUT2(), .CLKOUT3(), .CLKOUT4(), .CLKOUT5()
);
// end insert

BUFG U_FB (.I(fbout), .O(fbin));
BUFG U_PLL_BUFG (.I(dclk_pll), .O(dclk));
BUFG U_DCLK_BUFG (.I(dclk_in),.O(dclk));

/*******************************************************************************

5. If using linux - run "make -f ibert.mak"

If using Windows - Create and run an ibert.bat file in the ibertgtp_temp directory that has the following commands -

xst -intstyle silent -ifn ibert_drp_wrap.xst
xst -intstyle silent -ifn ibert_top.xst
ngdbuild -intstyle silent -uc ibert_top.ucf -p 5vsx35t-3ff665 ibert_top
map -intstyle silent -w -ol high -cm speed -o ibert_top.map.ncd ibert_top.ngd
par -intstyle silent -w -ol high ibert_top.map.ncd ibert_top.ncd
bitgen -intstyle silent -d -w -g StartUpClk:JTAGCLK -g UnusedPin:Pullnone ibert_top.ncd ibert.bit

AR# 31685
Date Created 10/02/2008
Last Updated 12/15/2012
Status Active
Type General Article