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AR# 31702

LogiCORE XAUI v7.3rev1 and v7.4 - When using Virtex-4 GT11 Max skew and delay constraints needed for inverted GREFCLK


It was found that under some circumstances output skew between the TX lanes when using the GT11 can be large. This is solved by inverting GREFCLK. Max delay constraints should be added to the ucf for this clock.


The following constraints should be added to the ucf to insure that the inverter for the GREFCLK is placed in an optimal location and there is not excessive delay on the GREFCLK net:

NET clk78_dcm MAXDELAY = 2 ns;

NET clk78_inv MAXDELAY = 2 ns;

AR# 31702
Date Created 09/17/2008
Last Updated 12/15/2012
Status Active
Type General Article