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AR# 31756

10.1 EDK, PPC440MC_DDR2 - Controller with -1 speed grade fails timing at 200 MHz

Description

Keyword: MPMC, DDR2 controller, Virtex-5 FXT, PPC 440

I created a system using Base System Builder for the ML510 board, and then changed the device speed grade to -1 (default is -2). The DDR2 frequency is 200 MHz, but the generated design fails timing.

The PPC440MC_DDR2 specifies a maximum frequency of 267 MHz for a -1 device. How do I meet 200 MHz timing?

Solution

One of the "FROM TO" timing constraints in the UCF can be relaxed when running slower than 267 MHz.

Look for the following constraints in the UCF file:

###########################################################################

## Half-cycle path constraint from IDDR to CE pin for all DQ IDDRs

## for DQS Read Postamble Glitch Squelch circuit

###########################################################################

## Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack

## where slack account for rise-time of DQS on board. For now assume slack =

## 0.400ns (based on initial SPICE simulations, assumes use of ODT), so

## time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz

INST "DDR2_SDRAM_DIMM0*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";

INST "DDR2_SDRAM_DIMM0*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";

TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;

For a 200 MHz memory clock, a 5ns period: 0.4*Tcyc + 0.40ns = 0.4*(5 ns) + 0.40ns = 2.4ns.

Thus, the "From-to" constraint can be relaxed to 2.4ns when running at 200 MHz.

AR# 31756
Date Created 10/02/2008
Last Updated 12/15/2012
Status Active
Type General Article